ARLGJan 17, 2024

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators

arXiv:2401.09509v123 citationsh-index: 20ISQED
Originality Incremental advance
AI Analysis

This work addresses reliability challenges in specialized DNN accelerators for safety-critical domains, though it appears incremental as it builds on existing quantization and fault analysis methods.

The paper tackles the trade-off between hardware performance and reliability in DNN accelerators, particularly for safety-critical applications, by introducing an automated framework that analyzes the impact of quantization on model accuracy, activation fault reliability, and hardware efficiency, with experiments on benchmarks showing profound implications.

The stringent requirements for the Deep Neural Networks (DNNs) accelerator's reliability stand along with the need for reducing the computational burden on the hardware platforms, i.e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators. Moreover, the growing demand for specialized DNN accelerators with tailored requirements, particularly for safety-critical applications, necessitates a comprehensive design space exploration to enable the development of efficient and robust accelerators that meet those requirements. Therefore, the trade-off between hardware performance, i.e. area and delay, and the reliability of the DNN accelerator implementation becomes critical and requires tools for analysis. This paper presents a comprehensive methodology for exploring and enabling a holistic assessment of the trilateral impact of quantization on model accuracy, activation fault reliability, and hardware efficiency. A fully automated framework is introduced that is capable of applying various quantization-aware techniques, fault injection, and hardware implementation, thus enabling the measurement of hardware parameters. Moreover, this paper proposes a novel lightweight protection technique integrated within the framework to ensure the dependable deployment of the final systolic-array-based FPGA implementation. The experiments on established benchmarks demonstrate the analysis flow and the profound implications of quantization on reliability, hardware performance, and network accuracy, particularly concerning the transient faults in the network's activations.

Foundations

The foundational work for this paper's niche, ranked by how specifically the neighbourhood builds on it — not by global fame.

Your Notes