Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
This work addresses the challenge of generating compilable and PPA-optimized RTL code for hardware design engineers, representing an incremental improvement over existing LLM-based methods.
The paper tackled the problem of generating high-quality register transfer level (RTL) code using large language models (LLMs), which often produce code with compilation failures and suboptimal power, performance, and area (PPA) efficiency. The result was an automated transformer decoding algorithm that integrated Monte Carlo tree-search, achieving a 31.8% improvement in area-delay product for a 16-bit adder compared to state-of-the-art LLMs.
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.