A Lightweight Inception Boosted U-Net Neural Network for Routability Prediction
This work addresses the critical need for efficient and accurate routability prediction in AI-assisted electronic design automation, representing an incremental improvement with specific gains in a domain-specific context.
The paper tackles the problem of predicting routing congestion and design rule checking hotspots in VLSI circuit design by proposing a novel U-Net variant boosted with an Inception module, achieving up to 5% and 20% reductions in Avg-NRMSE for RC and DRC, respectively, and outperforming prior models on SSIM metrics.
As the modern CPU, GPU, and NPU chip design complexity and transistor counts keep increasing, and with the relentless shrinking of semiconductor technology nodes to nearly 1 nanometer, the placement and routing have gradually become the two most pivotal processes in modern very-large-scale-integrated (VLSI) circuit back-end design. How to evaluate routability efficiently and accurately in advance (at the placement and global routing stages) has grown into a crucial research area in the field of artificial intelligence (AI) assisted electronic design automation (EDA). In this paper, we propose a novel U-Net variant model boosted by an Inception embedded module to predict Routing Congestion (RC) and Design Rule Checking (DRC) hotspots. Experimental results on the recently published CircuitNet dataset benchmark show that our proposed method achieves up to 5% (RC) and 20% (DRC) rate reduction in terms of Avg-NRMSE (Average Normalized Root Mean Square Error) compared to the classic architecture. Furthermore, our approach consistently outperforms the prior model on the SSIM (Structural Similarity Index Measure) metric.