Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
This addresses a critical problem for developers of ML hardware accelerators by offering a potential solution to scalability and efficiency limitations, though it appears incremental as it builds on existing 2.5D architectures with optical enhancements.
The paper tackles the communication bottleneck in scale-out machine learning hardware accelerators by proposing silicon photonic 2.5D interposer networks to replace slow metallic interconnects, aiming to achieve energy-efficient and high-throughput architectures.
Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.