Learning-driven Physically-aware Large-scale Circuit Gate Sizing
This addresses timing optimization bottlenecks for large-scale circuit designers, representing a domain-specific incremental improvement over existing ML-based methods.
The authors tackled the problem of suboptimal and inefficient gate sizing in circuit timing optimization by developing a learning-driven physically-aware framework that simultaneously optimizes multiple timing paths while considering layout constraints. Their approach achieved higher timing performance improvements faster than commercial tools.
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.