AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
This work addresses the challenge of accelerating hardware design optimization for engineers using HLS, though it appears incremental as it builds on existing methods like DNNs and BO.
The paper tackles the time-consuming problem of exploring design space parameters in high-level synthesis (HLS) for hardware engineers by proposing AutoHLS, a framework that integrates deep neural networks with Bayesian optimization, resulting in up to a 70-fold speedup in exploration time.
High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space parameters can take much time and effort for hardware engineers to meet specific design specifications. This paper proposes a novel framework called AutoHLS, which integrates a deep neural network (DNN) with Bayesian optimization (BO) to accelerate HLS hardware design optimization. Our tool focuses on HLS pragma exploration and operation transformation. It utilizes integrated DNNs to predict synthesizability within a given FPGA resource budget. We also investigate the potential of emerging quantum neural networks (QNNs) instead of classical DNNs for the AutoHLS pipeline. Our experimental results demonstrate up to a 70-fold speedup in exploration time.