Mapping Image Transformations Onto Pixel Processor Arrays
This provides foundational building blocks for visual tasks on PPA architectures, serving as a reference for future research, but it is incremental as it adapts existing transformations to a new hardware platform.
The paper tackled the problem of performing image transformations like shearing, rotation, and scaling directly on Pixel Processor Arrays (PPA), demonstrating implementations on a 256x256 array with minimized SIMD instructions.
Pixel Processor Arrays (PPA) present a new vision sensor/processor architecture consisting of a SIMD array of processor elements, each capable of light capture, storage, processing and local communication. Such a device allows visual data to be efficiently stored and manipulated directly upon the focal plane, but also demands the invention of new approaches and algorithms, suitable for the massively-parallel fine-grain processor arrays. In this paper we demonstrate how various image transformations, including shearing, rotation and scaling, can be performed directly upon a PPA. The implementation details are presented using the SCAMP-5 vision chip, that contains a 256x256 pixel-parallel array. Our approaches for performing the image transformations efficiently exploit the parallel computation in a cellular processor array, minimizing the number of SIMD instructions required. These fundamental image transformations are vital building blocks for many visual tasks. This paper aims to serve as a reference for future PPA research while demonstrating the flexibility of PPA architectures.