Neuroevolving Electronic Dynamical Networks
This addresses a computational bottleneck for researchers and practitioners in evolutionary algorithms and neural networks, though it is incremental as it applies existing FPGA technology to a known problem.
The paper tackles the problem of time-consuming fitness evaluation in neuroevolution for continuous time recurrent neural networks (CTRNNs) by using field programmable gate arrays (FPGAs) with dynamic and partial reconfiguration, resulting in acceleration of the process by several orders of magnitude and faster convergence to optimal solutions.
Neuroevolution is a powerful method of applying an evolutionary algorithm to refine the performance of artificial neural networks through natural selection; however, the fitness evaluation of these networks can be time-consuming and computationally expensive, particularly for continuous time recurrent neural networks (CTRNNs) that necessitate the simulation of differential equations. To overcome this challenge, field programmable gate arrays (FPGAs) have emerged as an increasingly popular solution, due to their high performance and low power consumption. Further, their ability to undergo dynamic and partial reconfiguration enables the extremely rapid evaluation of the fitness of CTRNNs, effectively addressing the bottleneck associated with conventional methods of evolvable hardware. By incorporating fitness evaluation directly upon the programmable logic of the FPGA, hyper-parallel evaluation becomes feasible, dramatically reducing the time required for assessment. This inherent parallelism of FPGAs accelerates the entire neuroevolutionary process by several orders of magnitude, facilitating faster convergence to an optimal solution. The work presented in this study demonstrates the potential of utilizing dynamic and partial reconfiguration on capable FPGAs as a powerful platform for neuroevolving dynamic neural networks.