A Multi-Expert Large Language Model Architecture for Verilog Code Generation
This addresses the challenge of automated hardware design for engineers, but appears incremental as it builds on existing LLM approaches with a specialized architecture.
The paper tackles the problem of low-quality Verilog code generation by large language models, introducing a multi-expert LLM architecture that improves the percentage of syntactically and functionally correct outputs.
Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality of the generated Verilog code. To address such limitations, this paper introduces an innovative multi-expert LLM architecture for Verilog code generation (MEV-LLM). Our architecture uniquely integrates multiple LLMs, each specifically fine-tuned with a dataset that is categorized with respect to a distinct level of design complexity. It allows more targeted learning, directly addressing the nuances of generating Verilog code for each category. Empirical evidence from experiments highlights notable improvements in terms of the percentage of generated Verilog outputs that are syntactically and functionally correct. These findings underscore the efficacy of our approach, promising a forward leap in the field of automated hardware design through machine learning.