KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology
This work addresses the problem of inefficient and circuit-specific optimization for circuit designers, offering a transferable solution that is incremental in enhancing existing methods.
The paper tackles the challenge of automatic transistor sizing in circuit design by introducing KATO, which integrates knowledge alignment and transfer learning into Bayesian optimization, achieving up to 2x simulation reduction and 1.2x design improvement over baselines.
Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.