PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC
This work addresses the problem of adapting to diverse classification tasks with limited data for embedded systems, though it is incremental as it builds on existing frameworks like Tensil.
The paper tackles implementing few-shot learning on embedded FPGA SoCs by developing an end-to-end open-source pipeline for object classification, resulting in a demonstrator with 30 ms latency and 6.2 W power consumption on a PYNQ-Z1 board.
This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board.