Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
This work provides benchmarking insights for RISC-V researchers and developers, but it is incremental as it applies existing tools to a new architecture without major methodological innovations.
The study evaluated the performance of various machine learning inference workloads on RISC-V architectures using the gem5 simulator and an MLIR-based compilation toolchain, identifying limitations in gem5 for RISC-V simulation.
Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve as a dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement.