LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation
This work addresses efficiency challenges in analog circuit design automation, offering an incremental improvement over existing BO techniques.
The paper tackles the slow convergence and high data needs of Bayesian Optimization (BO) in analog layout synthesis by introducing the LLANA framework, which uses Large Language Models (LLMs) to enhance BO for generating design constraints, achieving performance comparable to state-of-the-art BO methods.
Analog layout synthesis faces significant challenges due to its dependence on manual processes, considerable time requirements, and performance instability. Current Bayesian Optimization (BO)-based techniques for analog layout synthesis, despite their potential for automation, suffer from slow convergence and extensive data needs, limiting their practical application. This paper presents the \texttt{LLANA} framework, a novel approach that leverages Large Language Models (LLMs) to enhance BO by exploiting the few-shot learning abilities of LLMs for more efficient generation of analog design-dependent parameter constraints. Experimental results demonstrate that \texttt{LLANA} not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space, thanks to LLM's superior contextual understanding and learning efficiency. The code is available at https://github.com/dekura/LLANA.