Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices
This work addresses the problem of efficient neural network deployment for ultra-low-power devices, representing an incremental improvement in optimization techniques.
The paper tackled the challenge of deploying depthwise separable convolutions on ultra-low-power devices by exploring kernel fusion and data layout optimizations to reduce memory transfers, resulting in up to 11.40% latency reduction and up to 52.97% reduction in activation data movements on the GAP8 SoC.
Depthwise separable convolutions are a fundamental component in efficient Deep Neural Networks, as they reduce the number of parameters and operations compared to traditional convolutions while maintaining comparable accuracy. However, their low data reuse opportunities make deploying them notoriously difficult. In this work, we perform an extensive exploration of alternatives to fuse the depthwise and pointwise kernels that constitute the separable convolutional block. Our approach aims to minimize time-consuming memory transfers by combining different data layouts. When targeting a commercial ultra-low-power device with a three-level memory hierarchy, the GreenWaves GAP8 SoC, we reduce the latency of end-to-end network execution by up to 11.40%. Furthermore, our kernels reduce activation data movements between L2 and L1 memories by up to 52.97%.