ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
This work addresses security gaps in chip design automation for cryptographic hardware, offering a novel framework to enhance resilience against side-channel attacks.
The paper tackled the problem of power side-channel (PSC) vulnerabilities in cryptographic hardware by proposing a 'security-first' approach during logic synthesis, resulting in a 120x speedup in PSC analysis and a 3.11x improvement in PSC resilience for state-of-the-art countermeasures.
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security arising from the design automation process. That is, automation traditionally prioritizes power, performance, and area (PPA), sidelining security. We propose a "security-first" approach, refining the logic synthesis stage to enhance the overall resilience of PSC countermeasures. We introduce ASCENT, a learning-and-search-based framework that (i) drastically reduces the time for post-design PSC evaluation and (ii) explores the security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of a large number of candidate netlists, leading to an improvement in PSC resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x faster than traditional PSC analysis and yields a 3.11x improvement for PSC resilience of state-of-the-art PSC countermeasures