CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis
This addresses circuit design automation for electronics engineers, but appears incremental as it builds on existing LLM methods.
The paper tackles the problem of automated circuit topology synthesis by introducing CIRCUITSYNTH, which uses large language models to generate valid circuit configurations, showing effectiveness compared to fine-tuned LLM variants.
Circuit topology generation plays a crucial role in the design of electronic circuits, influencing the fundamental functionality of the circuit. In this paper, we introduce CIRCUITSYNTH, a novel approach that harnesses LLMs to facilitate the automated synthesis of valid circuit topologies. With a dataset comprising both valid and invalid circuit configurations, CIRCUITSYNTH employs a sophisticated two-phase methodology, comprising Circuit Topology Generation and Circuit Topology Refinement. Experimental results demonstrate the effectiveness of CIRCUITSYNTH compared to various fine-tuned LLM variants. Our approach lays the foundation for future research aimed at enhancing circuit efficiency and specifying output voltage, thus enabling the automated generation of circuit topologies with improved performance and adherence to design requirements.