DeepGate3: Towards Scalable Circuit Representation Learning
This addresses scalability issues in circuit representation learning for Electronic Design Automation, though it appears incremental as an enhancement to the DeepGate family.
The paper tackles the scalability limitations of GNN-based circuit representation learning in EDA by introducing DeepGate3, which integrates Transformer modules with GNNs and novel supervision tasks, resulting in marked improvements in scalability and generalizability over existing approaches.
Circuit representation learning has shown promising results in advancing the field of Electronic Design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology.