Are LLMs Any Good for High-Level Synthesis?
It addresses the need for faster, energy-efficient hardware design methods, particularly for AI acceleration and embedded systems, but is incremental as it surveys and experiments with existing approaches.
This paper investigates whether Large Language Models (LLMs) can streamline or replace High-Level Synthesis (HLS) for hardware design by comparing Verilog designs from standard HLS tools and LLMs based on performance, power, and resource utilization metrics.
The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.