Fire-Flyer AI-HPC: A Cost-Effective Software-Hardware Co-Design for Deep Learning
This addresses cost and energy efficiency problems for AI-HPC users, though it appears incremental as it builds on existing hardware with optimizations.
The paper tackles the high computational and bandwidth demands in deep learning by introducing the Fire-Flyer AI-HPC architecture, a hardware-software co-design that achieved performance similar to DGX-A100 while reducing costs by 50% and energy consumption by 40% using 10,000 PCIe A100 GPUs.
The rapid progress in Deep Learning (DL) and Large Language Models (LLMs) has exponentially increased demands of computational power and bandwidth. This, combined with the high costs of faster computing chips and interconnects, has significantly inflated High Performance Computing (HPC) construction costs. To address these challenges, we introduce the Fire-Flyer AI-HPC architecture, a synergistic hardware-software co-design framework and its best practices. For DL training, we deployed the Fire-Flyer 2 with 10,000 PCIe A100 GPUs, achieved performance approximating the DGX-A100 while reducing costs by half and energy consumption by 40%. We specifically engineered HFReduce to accelerate allreduce communication and implemented numerous measures to keep our Computation-Storage Integrated Network congestion-free. Through our software stack, including HaiScale, 3FS, and HAI-Platform, we achieved substantial scalability by overlapping computation and communication. Our system-oriented experience from DL training provides valuable insights to drive future advancements in AI-HPC.