PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
This addresses a practical problem for VLSI design and manufacturing by enabling scalable pattern generation without large datasets, though it is incremental as it builds on existing diffusion and inpainting methods.
The paper tackles the challenge of generating diverse VLSI layout patterns with limited training data for new technology nodes, proposing PatternPaint, a diffusion-based inpainting framework that achieves high diversity and legality rates, including a 1.87X improvement in legality with few-shot finetuning.
Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate with 1.87X improvement compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.