VLSI Hypergraph Partitioning with Deep Learning
This work addresses chip design efficiency for VLSI engineers, but it is incremental as it focuses on benchmarking and evaluating existing methods rather than introducing new techniques.
The study tackled the problem of VLSI hypergraph partitioning by evaluating deep learning methods, particularly GNNs, on new synthetic benchmarks that mimic real-world netlists, finding that these methods show promise but have not been fully explored in this context, with results compared to existing state-of-the-art algorithms.
Partitioning is a known problem in computer science and is critical in chip design workflows, as advancements in this area can significantly influence design quality and efficiency. Deep Learning (DL) techniques, particularly those involving Graph Neural Networks (GNNs), have demonstrated strong performance in various node, edge, and graph prediction tasks using both inductive and transductive learning methods. A notable area of recent interest within GNNs are pooling layers and their application to graph partitioning. While these methods have yielded promising results across social, computational, and other random graphs, their effectiveness has not yet been explored in the context of VLSI hypergraph netlists. In this study, we introduce a new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality. We distinguish these benchmarks with the prior work and evaluate existing state-of-the-art partitioning algorithms alongside GNN-based approaches, highlighting their respective advantages and disadvantages.