The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
This work addresses a domain-specific bottleneck for circuit designers by providing a faster alternative to traditional methods, though it is incremental as it builds on existing LLM and GNN techniques.
The paper tackles the problem of computationally intensive logic synthesis in circuit design by augmenting large language models (LLMs) with predictor networks and graph neural network (GNN) embeddings to estimate circuit quality directly from HDL code, achieving superior performance on the OpenABCD benchmark.
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Recent advancements in large language models (LLMs), particularly those fine-tuned on programming languages, present a promising alternative. This work proposes augmenting LLMs with predictor networks trained to estimate circuit quality directly from HDL code. To enhance performance, the model is regularized using embeddings from graph neural networks (GNNs) trained on Look-Up Table (LUT) graphs, thereby incorporating lower-level circuit insights. The proposed method demonstrates superior performance compared to existing graph-based RTL-level estimation techniques on the established benchmark OpenABCD, while providing instant feedback on HDL code quality.