Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM
This work addresses verification challenges for hardware engineers, but it appears incremental as it builds on existing methodologies like UVM.
The paper tackles the problem of verifying complex mathematical algorithms in hardware by presenting pragmatic solutions that maximize leverage of a known-answer-test strategy, demonstrating early bug detection based on real project experience with single chip radar sensors.
This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner. Maximizing leverage of a known-answer-test strategy, based on predefined data scenarios combined with design-for-verification modes, we demonstrate how to find and isolate concept and design bugs early in the flow. The solutions presented are based on real project experience with single chip radar sensors for a variety of applications. The verification environments supporting the presented strategies are based on SystemVerilog and the Universal Verification Methodology.