HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
This addresses the problem of scalable chip design for hardware engineers by enabling more reliable and efficient Verilog generation through hierarchical decomposition, though it appears incremental as it builds on existing LLM capabilities with specific enhancements.
The paper tackles the problem of LLMs generating single code blocks rather than hierarchical structures for hardware designs, which causes hallucinations in complex designs like Domain-Specific Accelerators, by proposing HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes tasks into manageable submodules and integrates automatic Design Space Exploration, weight-based retrieval, and real-time human-computer interaction, resulting in significantly improved design quality.
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.