A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
This addresses energy efficiency constraints in edge computing or low-power AI hardware, though it appears incremental as it builds on existing ReRAM analog computing methods.
This work tackled the problem of energy and area inefficiency in ReRAM-based accelerators for neural networks by proposing a fully hardware-implemented design that eliminates DACs, ADCs, and explicit activation function components, achieving improved performance metrics without accuracy loss.
Emerging ReRAM-based accelerators process neural networks via analog Computing-in-Memory (CiM) for ultra-high energy efficiency. However, significant overhead in peripheral circuits and complex nonlinear activation modes constrain system energy efficiency improvements. This work explores the hardware implementation of the Sigmoid and SoftMax activation functions of neural networks with stochastically binarized neurons by utilizing sampled noise signals from ReRAM devices to achieve a stochastic effect. We propose a complete ReRAM-based Analog Computing Accelerator (RACA) that accelerates neural network computation by leveraging stochastically binarized neurons in combination with ReRAM crossbars. The novel circuit design removes significant sources of energy/area efficiency degradation, i.e., the Digital-to-Analog and Analog-to-Digital Converters (DACs and ADCs) as well as the components to explicitly calculate the activation functions. Experimental results show that our proposed design outperforms traditional architectures across all overall performance metrics without compromising inference accuracy.