Aligning Netlist to Source Code using SynAlign
This addresses a bottleneck for chip designers by enabling early feedback on timing and power, though it is incremental as it builds on existing design structures without altering compilers or synthesis processes.
The paper tackles the problem of lost correlation between gate-level netlists and source code in chip design by introducing SynAlign, an automated alignment tool that maintains this correlation across tools and tolerates up to 61% design net changes without affecting accuracy.
In current chip design processes, using multiple tools to obtain a gate-level netlist often results in the loss of source code correlation. SynAlign addresses this challenge by automating the alignment process, simplifying iterative design, reducing overhead, and maintaining correlation across various tools. This enhances the efficiency and effectiveness of chip design workflows. Improving characteristics such as frequency through iterative design is essential for enhancing accelerators and chip designs. While synthesis tools produce netlists with critical path information, designers often lack the tools to trace these netlist cells back to their original source code. Mapping netlist components to source code provides early feedback on timing and power for frontend designers. SynAlign automatically aligns post-optimized netlists with the original source code without altering compilers or synthesis processes. Its alignment strategy relies on the consistent design structure throughout the chip design cycle, even with changes in compiler flow. This consistency allows engineers to maintain a correlation between modified designs and the original source code across various tools. Remarkably, SynAlign can tolerate up to 61\% design net changes without impacting alignment accuracy.