A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs
This addresses a problem for developers in data centers using FPGA accelerators, offering a practical tool to speed up the development process, though it appears incremental as it builds on existing co-simulation concepts.
The paper tackled the challenge of slow and difficult joint development and debugging of host software and FPGA hardware in PCIe-connected FPGA systems, by designing a VM-HDL co-simulation framework that provides full visibility and significantly shorter debug iterations.
PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations.