Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators
This addresses scalability and versatility issues for AI hardware developers, but it is incremental as it builds on existing multi-chiplet approaches.
The paper tackles the problem of rigid and inefficient chip-to-chip interconnects in multi-chiplet AI accelerators by exploring wireless technology as a complement to wired interconnects, resulting in average speedups of 10% and maximum of 20%.
The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflicts with the need for scalable and versatile architectures capable of catering to the needs of the evolving and heterogeneous pool of Machine Learning (ML) models in the literature. In this context, multi-chiplet architectures assembling multiple (perhaps heterogeneous) accelerators are an appealing option that is unfortunately hindered by the still rigid and inefficient chip-to-chip interconnects. In this paper, we explore the potential of wireless technology as a complement to existing wired interconnects in this multi-chiplet approach. Using an evaluation framework from the state-of-the-art, we show that wireless interconnects can lead to speedups of 10% on average and 20% maximum. We also highlight the importance of load balancing between the wired and wireless interconnects, which will be further explored in future work.