EDocNet: Efficient Datasheet Layout Analysis Based on Focus and Global Knowledge Distillation
This work addresses a domain-specific problem for engineers in circuit design by providing an incremental improvement in document parsing efficiency.
The paper tackled the problem of inefficient manual browsing of electronic device documents by engineers, proposing EDocNet for automated layout analysis, which achieved better average accuracy and recall while significantly increasing model checking speed.
When designing circuits, engineers obtain the information of electronic devices by browsing a large number of documents, which is low efficiency and heavy workload. The use of artificial intelligence technology to automatically parse documents can greatly improve the efficiency of engineers. However, the current document layout analysis model is aimed at various types of documents and is not suitable for electronic device documents. This paper proposes to use EDocNet to realize the document layout analysis function for document analysis, and use the electronic device document data set created by myself for training. The training method adopts the focus and global knowledge distillation method, and a model suitable for electronic device documents is obtained, which can divide the contents of electronic device documents into 21 categories. It has better average accuracy and average recall rate. It also greatly improves the speed of model checking.