FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference
This addresses reliability issues in DNN hardware for mission-critical applications, representing an incremental improvement with specific resource and performance gains.
The paper tackles the problem of improving reliability for DNN inference on systolic arrays by proposing a reconfigurable architecture with multiple execution modes, achieving up to 3x speedup, 6x fewer resources than static redundancy, and 2.5x fewer resources than prior solutions for transient faults.
The emergence of Deep Neural Networks (DNNs) in mission- and safety-critical applications brings their reliability to the front. High performance demands of DNNs require the use of specialized hardware accelerators. Systolic array architecture is widely used in DNN accelerators due to its parallelism and regular structure. This work presents a run-time reconfigurable systolic array architecture with three execution modes and four implementation options. All four implementations are evaluated in terms of resource utilization, throughput, and fault tolerance improvement. The proposed architecture is used for reliability enhancement of DNN inference on systolic array through heterogeneous mapping of different network layers to different execution modes. The approach is supported by a novel reliability assessment method based on fault propagation analysis. It is used for the exploration of the appropriate execution mode--layer mapping for DNN inference. The proposed architecture efficiently protects registers and MAC units of systolic array PEs from transient and permanent faults. The reconfigurability feature enables a speedup of up to $3\times$, depending on layer vulnerability. Furthermore, it requires $6\times$ fewer resources compared to static redundancy and $2.5\times$ fewer resources compared to the previously proposed solution for transient faults.