AI-Driven Optimization of Hardware Overlay Configurations
This work addresses a domain-specific problem for FPGA designers, offering an incremental improvement over existing optimization methods.
The paper tackles the problem of optimizing FPGA overlay configurations, which traditionally requires time-consuming trial-and-error iterations, by using a Random Forest regression model to predict feasibility and efficiency before hardware compilation. The result is a significant reduction in required iterations with high prediction accuracy that closely matches actual resource usage.
Designing and optimizing FPGA overlays is a complex and time-consuming process, often requiring multiple trial-and-error iterations to determine a suitable configuration. This paper presents an AI-driven approach to optimizing FPGA overlay configurations, specifically focusing on the NAPOLY+ automata processor implemented on the ZCU104 FPGA. By leveraging machine learning techniques, particularly Random Forest regression, we predict the feasibility and efficiency of different configurations before hardware compilation. Our method significantly reduces the number of required iterations by estimating resource utilization, including logical elements, distributed memory, and fanout, based on historical design data. Experimental results demonstrate that our model achieves high prediction accuracy, closely matching actual resource usage while accelerating the design process.