ML For Hardware Design Interpretability: Challenges and Opportunities
This addresses the time-consuming manual process for hardware engineers designing custom accelerators for ML workloads, but it is incremental as it reviews and guides rather than presents new results.
The paper tackles the problem of automating hardware design interpretability, specifically generating natural language descriptions from RTL code, to accelerate the design of custom ML hardware accelerators, by reviewing LLM adaptations, highlighting challenges, and identifying opportunities for future research.
The increasing size and complexity of machine learning (ML) models have driven the growing need for custom hardware accelerators capable of efficiently supporting ML workloads. However, the design of such accelerators remains a time-consuming process, heavily relying on engineers to manually ensure design interpretability through clear documentation and effective communication. Recent advances in large language models (LLMs) offer a promising opportunity to automate these design interpretability tasks, particularly the generation of natural language descriptions for register-transfer level (RTL) code, what we refer to as "RTL-to-NL tasks." In this paper, we examine how design interpretability, particularly in RTL-to-NL tasks, influences the efficiency of the hardware design process. We review existing work adapting LLMs for these tasks, highlight key challenges that remain unaddressed, including those related to data, computation, and model development, and identify opportunities to address them. By doing so, we aim to guide future research in leveraging ML to automate RTL-to-NL tasks and improve hardware design interpretability, thereby accelerating the hardware design process and meeting the increasing demand for custom hardware accelerators in machine learning and beyond.