A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning
This work addresses hardware efficiency for probabilistic computing in AI applications, though it appears incremental as it builds on existing physics-inspired solvers with chip-specific optimizations.
The paper tackles the challenge of implementing probabilistic computing in hardware by developing a CMOS chip with 440 spins in a Chimera graph on 0.44 mm², using a hardware-aware algorithm to mitigate process variations, and validates it on tasks like logic gates and MaxCut.
This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications.