From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
For IC verification engineers, UVM^2 significantly reduces manual effort and improves coverage, but the approach is incremental as it applies LLMs to a known bottleneck.
UVM^2 automates UVM testbench generation and refinement using LLMs, reducing setup time by up to 90% compared to experienced engineers and achieving 87.44% code coverage and 89.58% function coverage, outperforming prior work by 20.96% and 23.51% respectively.
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology (UVM) is widely used in industry to improve verification efficiency through structured and reusable testbenches, constructing these testbenches and generating sufficient stimuli remain challenging. These challenges arise from the considerable manual coding effort required, repetitive manual execution of multiple EDA tools, and the need for in-depth domain expertise to navigate complex designs.Here, we present UVM^2, an automated verification framework that leverages Large Language Models (LLMs) to generate UVM testbenches and iteratively refine them using coverage feedback, significantly reducing manual effort while maintaining rigorous verification standards.To evaluate UVM^2, we introduce a benchmark suite comprising Register Transfer Level (RTL) designs of up to 1.6K lines of code.The results show that UVM^2 reduces testbench setup time by up to UVM^2 compared to experienced engineers, and achieve average code and function coverage of 87.44% and 89.58%, outperforming state-of-the-art solutions by 20.96% and 23.51%, respectively.