LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning
This work addresses the problem of automating FPGA optimization for datacenter environments, representing a novel method for a known bottleneck in HLS tools.
The paper tackles the challenge of requiring expert knowledge to manually insert optimization pragmas for high-performance FPGA programming via High-Level Synthesis (HLS), proposing LIFT, an LLM-based assistant that automatically generates these pragmas, resulting in average performance improvements of 3.52x over prior state-of-the-art AutoDSE, 2.16x over HARP, and 66x over GPT-4o.
FPGAs are increasingly adopted in datacenter environments for their reconfigurability and energy efficiency. High-Level Synthesis (HLS) tools have eased FPGA programming by raising the abstraction level from RTL to untimed C/C++, yet attaining high performance still demands expert knowledge and iterative manual insertion of optimization pragmas to modify the microarchitecture. To address this challenge, we propose LIFT, a large language model (LLM)-based coding assistant for HLS that automatically generates performance-critical pragmas given a C/C++ design. We fine-tune the LLM by tightly integrating and supervising the training process with a graph neural network (GNN), combining the sequential modeling capabilities of LLMs with the structural and semantic understanding of GNNs necessary for reasoning over code and its control/data dependencies. On average, LIFT produces designs that improve performance by 3.52x and 2.16x than prior state-of the art AutoDSE and HARP respectively, and 66x than GPT-4o.