CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures
This work addresses a domain-specific problem for researchers and designers in hardware acceleration by providing an accessible platform for design space exploration, though it appears incremental as it builds on existing CIM concepts.
The paper tackles the lack of comprehensive tools for developing and optimizing digital Compute-in-Memory (CIM) architectures for DNN acceleration, resulting in CIMFlow, an integrated framework that enables systematic prototyping and optimization across diverse configurations.
Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.