FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review
It addresses the computational demands of CNNs for researchers and practitioners, but is incremental as it is a review paper.
This paper reviews FPGA-based hardware accelerators for Convolutional Neural Networks, summarizing performance evaluation frameworks and comparing architectures in terms of latency, throughput, efficiency, power, and resource utilization.
Convolutional Neural Networks (CNNs) are fundamental to deep learning, driving applications across various domains. However, their growing complexity has significantly increased computational demands, necessitating efficient hardware accelerators. Field-Programmable Gate Arrays (FPGAs) have emerged as a leading solution, offering reconfigurability, parallelism, and energy efficiency. This paper provides a comprehensive review of FPGA-based hardware accelerators specifically designed for CNNs. It presents and summarizes the performance evaluation framework grounded in existing studies and explores key optimization strategies, such as parallel computing, dataflow optimization, and hardware-software co-design. It also compares various FPGA architectures in terms of latency, throughput, compute efficiency, power consumption, and resource utilization. Finally, the paper highlights future challenges and opportunities, emphasizing the potential for continued innovation in this field.