POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
This work addresses the problem of efficient and adaptive AI acceleration for edge computing platforms, offering a scalable solution that is incremental in its hardware-software co-design approach.
The paper tackles the need for flexible hardware to support diverse precision formats on energy-constrained edge platforms by presenting PARV-CE, a multi-precision MAC engine that achieves up to 2x improvement in PDP and 3x reduction in resource usage compared to state-of-the-art designs while maintaining accuracy within 1.8% of an FP32 baseline.
The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work presents PARV-CE, a SIMD-enabled, multi-precision MAC engine that performs efficient multiply-accumulate operations using a unified data-path for 4/8/16-bit fixed-point, floating point, and posit formats. The architecture incorporates a layer adaptive precision strategy to align computational accuracy with workload sensitivity, optimizing both performance and energy usage. PARV-CE integrates quantization-aware execution with a reconfigurable SIMD pipeline, enabling high-throughput processing with minimal overhead through hardware-software co-design. The results demonstrate up to 2x improvement in PDP and 3x reduction in resource usage compared to SoTA designs, while retaining accuracy within 1.8% FP32 baseline. The architecture supports both on-device training and inference across a range of workloads, including DNNs, RNNs, RL, and Transformer models. The empirical analysis establish PARVCE incorporated POLARON as a scalable and energy-efficient solution for precision-adaptive AI acceleration at edge.