Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons
This work addresses energy efficiency in neuromorphic hardware design, offering incremental insights for researchers and engineers in the field.
This paper compared event-driven and clock-driven spiking neuron models for hardware acceleration, evaluating them on FPGA to analyze trade-offs in latency, power, and energy efficiency, providing guidelines for energy-efficient neuromorphic systems.
This paper presents a comprehensive evaluation of Spiking Neural Network (SNN) neuron models for hardware acceleration by comparing event driven and clock-driven implementations. We begin our investigation in software, rapidly prototyping and testing various SNN models based on different variants of the Leaky Integrate and Fire (LIF) neuron across multiple datasets. This phase enables controlled performance assessment and informs design refinement. Our subsequent hardware phase, implemented on FPGA, validates the simulation findings and offers practical insights into design trade offs. In particular, we examine how variations in input stimuli influence key performance metrics such as latency, power consumption, energy efficiency, and resource utilization. These results yield valuable guidelines for constructing energy efficient, real time neuromorphic systems. Overall, our work bridges software simulation and hardware realization, advancing the development of next generation SNN accelerators.