RCNet: $ΔΣ$ IADCs as Recurrent AutoEncoders
This work addresses hardware design trade-offs for analog-to-digital converters, offering incremental improvements in optimizing SNR versus area constraints.
The paper tackles the design of Delta-Sigma incremental ADCs by proposing RCNet, a deep learning model that optimizes signal-to-noise ratio (SNR) under hardware constraints, achieving >13-bit effective number of bits (ENOB) with less than 14pF total capacitor area at an oversampling ratio of 80 samples.
This paper proposes a deep learning model (RCNet) for Delta-Sigma ($ΔΣ$) ADCs. Recurrent Neural Networks (RNNs) allow to describe both modulators and filters. This analogy is applied to Incremental ADCs (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area. Focusing on DC conversion, our early results demonstrate that $SNR$ defined as an Effective Number Of Bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms of $SNR$ ($>$13bit) versus area constraints ($<$14pF total capacitor) at a given $OSR$ (80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom.