Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
This addresses the problem of complex hardware design verification for engineers, though it appears incremental as it builds on existing LLM and AI methods.
The paper tackles the tedious and time-consuming process of hardware design verification by introducing an agentic AI-based approach that integrates AI agents with human-in-the-loop intervention, achieving over 95% coverage on five open-source designs with reduced verification time.
Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach to the planning, development, execution, and sign-off of functionally correct hardware designs. This tedious process requires significant effort and time to ensure a bug-free tape-out. The field of Natural Language Processing has undergone a significant transformation with the advent of Large Language Models (LLMs). These powerful models, often referred to as Generative AI (GenAI), have revolutionized how machines understand and generate human language, enabling unprecedented advancements in a wide array of applications, including hardware design verification. This paper presents an agentic AI-based approach to hardware design verification, which empowers AI agents, in collaboration with Humain-in-the-Loop (HITL) intervention, to engage in a more dynamic, iterative, and self-reflective process, ultimately performing end-to-end hardware design and verification. This methodology is evaluated on five open-source designs, achieving over 95% coverage with reduced verification time while demonstrating superior performance, adaptability, and configurability.