Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems
This addresses power and speed constraints for on-device learning in neuromorphic computing, though it appears incremental as it builds on existing circuit designs.
The researchers tackled the need for efficient winner-take-all circuits in neuromorphic systems by proposing a configurable circuit that achieved 34.9 μW power dissipation and 10.4 ns latency while processing 1000 inputs.
Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $μ$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.