da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs
This work addresses area and latency constraints for deploying neural networks on FPGAs in high-energy physics, representing an incremental improvement in optimization methods.
The paper tackles the bottleneck of area utilization in deploying real-time neural networks on FPGAs for applications like the CERN Large Hadron Collider, proposing a distributed arithmetic algorithm that reduces on-chip resources by up to a third and lowers latency, enabling previously infeasible implementations.
Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic (DA) on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.