A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization
This work addresses the problem of complex compiler integration for hardware accelerators in edge computing, offering a more accessible solution for developers, though it is incremental as it builds on existing frameworks like TVM and CoSA.
The paper tackles the challenge of integrating custom deep learning accelerators into ML compilers by introducing a TVM-based approach that abstracts complexities and automates tensor scheduling, achieving performance comparable to a specialized manual toolchain on the Gemmini accelerator.
The growing adoption of domain-specific architectures in edge computing platforms for deep learning has highlighted the efficiency of hardware accelerators. However, integrating custom accelerators into modern machine learning (ML) compilers remains a complex challenge due to the need for significant modifications in compilation layers and specialized scheduling techniques. Existing frameworks offer partial solutions and require users to navigate intricate compiler internals. In this paper, we introduce a TVM-based compilation integration approach that targets GEMM-based deep learning accelerators. Our approach abstracts the complexities of compiler integration, enabling seamless integration of accelerators without requiring in-depth knowledge of the underlying compiler. Furthermore, we extend and incorporate design space exploration tools, specifically CoSA, to automate efficient tensor scheduling, accounting for factors such as uneven mapping and double buffering. Our framework is benchmarked on the Gemmini accelerator, demonstrating performance comparable to its specialized manually implemented toolchain.