GATMesh: Clock Mesh Timing Analysis using Graph Neural Networks
This addresses the challenge of efficient and accurate timing analysis for high-performance VLSI design, though it is an incremental improvement over existing methods.
The paper tackled the problem of slow and inaccurate clock mesh timing analysis in VLSI systems by proposing GATMesh, a Graph Neural Network-based framework that achieved an average delay error of 5.27ps and speed-ups of 47146x over SPICE simulations.
Clock meshes are essential in high-performance VLSI systems for minimizing skew and handling PVT variations, but analyzing them is difficult due to reconvergent paths, multi-source driving, and input mesh buffer skew. SPICE simulations are accurate but slow; yet simplified models miss key effects like slew and input skew. We propose GATMesh, a Graph Neural Network (GNN)-based framework that models the clock mesh as a graph with augmented structural and physical features. Trained on SPICE data, GATMesh achieves high accuracy with average delay error of 5.27ps on unseen benchmarks, while achieving speed-ups of 47146x over multi-threaded SPICE simulation.