SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST
This work addresses energy-efficient edge computing for image recognition, but it is incremental as it applies an existing framework to a standard dataset.
The paper tackled the problem of deploying Spiking Neural Networks (SNNs) on FPGAs for low-latency, energy-efficient edge inference, specifically for MNIST digit recognition, by using the Spiker+ framework to generate optimized accelerators and analyzing trade-offs.
Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.