RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
This addresses the need for better evaluation tools in hardware design automation, though it is incremental as it builds on existing benchmarking efforts.
The authors tackled the problem of evaluating Large Language Models for Verilog code generation by creating RealBench, a benchmark based on real-world IP designs with rigorous verification, and found that even top models like o1-preview achieved only 13.3% pass@1 on module-level tasks and 0% on system-level tasks.
The automatic generation of Verilog code using Large Language Models (LLMs) has garnered significant interest in hardware design automation. However, existing benchmarks for evaluating LLMs in Verilog generation fall short in replicating real-world design workflows due to their designs' simplicity, inadequate design specifications, and less rigorous verification environments. To address these limitations, we present RealBench, the first benchmark aiming at real-world IP-level Verilog generation tasks. RealBench features complex, structured, real-world open-source IP designs, multi-modal and formatted design specifications, and rigorous verification environments, including 100% line coverage testbenches and a formal checker. It supports both module-level and system-level tasks, enabling comprehensive assessments of LLM capabilities. Evaluations on various LLMs and agents reveal that even one of the best-performing LLMs, o1-preview, achieves only a 13.3% pass@1 on module-level tasks and 0% on system-level tasks, highlighting the need for stronger Verilog generation models in the future. The benchmark is open-sourced at https://github.com/IPRC-DIP/RealBench.