Wafer Defect Root Cause Analysis with Partial Trajectory Regression
This work addresses the problem of wafer defect root cause analysis for semiconductor manufacturing, representing an incremental improvement with a novel method for a known bottleneck.
The paper tackles the challenge of identifying upstream processes responsible for wafer defects by proposing a novel framework called Partial Trajectory Regression (PTR), which addresses limitations of conventional regression models in handling variable-length processing routes, and demonstrates its effectiveness using real wafer history data from the NY CREATES fab.
Identifying upstream processes responsible for wafer defects is challenging due to the combinatorial nature of process flows and the inherent variability in processing routes, which arises from factors such as rework operations and random process waiting times. This paper presents a novel framework for wafer defect root cause analysis, called Partial Trajectory Regression (PTR). The proposed framework is carefully designed to address the limitations of conventional vector-based regression models, particularly in handling variable-length processing routes that span a large number of heterogeneous physical processes. To compute the attribution score of each process given a detected high defect density on a specific wafer, we propose a new algorithm that compares two counterfactual outcomes derived from partial process trajectories. This is enabled by new representation learning methods, proc2vec and route2vec. We demonstrate the effectiveness of the proposed framework using real wafer history data from the NY CREATES fab in Albany.