ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
This work addresses efficiency issues in logic synthesis for electronic design automation, offering a domain-specific improvement.
The paper tackled the high computational demands of logic optimization operators in electronic design automation by using a classifier to prune unsuccessful cuts preemptively, resulting in a 3.9x average speedup compared to the state-of-the-art ABC implementation.
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9x on average compared with the state-of-the-art ABC implementation.