Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
This addresses the challenge of integrating pin assignment with modern constraints in floorplanning for VLSI design, offering a novel framework that improves layout quality.
The paper tackles the problem of floorplanning in VLSI physical design by simultaneously optimizing module placement and pin assignment under multiple constraints, resulting in an average 6.81% reduction in HPWL, 13.39% decrease in feedthrough wirelength, 16.36% reduction in feedthrough modules, and 21.21% drop in unplaced pins while maintaining zero whitespace.
Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of pre-placed modules. In addition, the assignment of pins on module boundaries significantly impacts the performance of subsequent stages, including detailed placement and routing. However, traditional floorplanners often overlook pin assignment with modern constraints during the floorplanning stage. In this work, we introduce Piano, a floorplanning framework that simultaneously optimizes module placement and pin assignment under multiple constraints. Specifically, we construct a graph based on the geometric relationships among modules and their netlist connections, then iteratively search for shortest paths to determine pin assignments. This graph-based method also enables accurate evaluation of feedthrough and unplaced pins, thereby guiding overall layout quality. To further improve the design, we adopt a whitespace removal strategy and employ three local optimizers to enhance layout metrics under multi-constraint scenarios. Experimental results on widely used benchmark circuits demonstrate that Piano achieves an average 6.81% reduction in HPWL, a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in the number of feedthrough modules, and a 21.21% drop in unplaced pins, while maintaining zero whitespace.